CS 208: Computer Organization and Architecture

Takehome exam: due 8:30AM Friday, April 25

This is a an exam. You may consult your notes, any book, and the Internet. You may not speak with any person other than Jeff Ondich, electronically or otherwise, about the content of this exam. If you obtain relevant information from any source other than yourself, cite your sources clearly.

Justify your answers. (Note that "justify your answers" implies "show your work.") Have fun.

  1. (N points) Consider the 32-bit number 0x216CFFE9. What does this number represent if you interpret it as:

    1. a two's complement integer?
    2. a MIPS instruction? (You may find this chart of op codes handy.)
    3. a sequence of four ISO-8859-1 characters?

  2. (N points) Some questions about integers.

    1. In base ten, what is the value of the largest 32-bit two's complement integer?
    2. In base ten, what is the value of the smallest 32-bit two's complement integer? (Note that "smallest" and "largest" refer to position on the number line so, for example, -2 is smaller than -1, and -1 is smaller than 3.)
    3. If you have a 32-bit two's complement integer N > 0, and 2*N is small enough to be representable as a 32-bit two's complement integer, then you can double N by shifting its two's complement representation left by one bit. Now, suppose N < 0. Does shifting left double N? If so, explain why. If not, give an example where it fails.

  3. (N points) Pseudoinstructions are assembly language instructions that are allowed in programs, but do not have corresponding machine language equivalents. When an assembler encounters a pseudoinstruction, it replaces that instruction with one or more real instructions before translating into machine language. For a very simple example, the MOVE $rt, $rs instruction in MIPS gets translated to ADD $rt, $rs, $zero, which in turn has a one-word machine language equivalent.

    1. Into what instruction(s) does the MARS assembler convert subiu $t0, $t1, 16? Then, assuming that $t0 and $t1 start out as 30 and 40 respectively, show what happens to all registers affected by the subiu pseudoinstruction during the execution of all the instructions that make up the subiu.
    2. This question turned out to be kind of weird, since observing the PC can modify it, and it changes anyway. Worth contemplating, but I wouldn't reuse this question on an exam. Someone asked in class the other day how you could access the PC (program counter) register, and I observed that there is no direct way to do so, but that there are indirect ways. Suppose you were writing a MIPS assembler and you wanted to add pseudoinstructions MOVEPC $rs (which copies the contents of $rs into the PC) and GETPC $rd (which copies the contents of the PC into $rd). Show what real instructions you would have your assembler convert these two pseudoinstructions into.
    3. Why do we have pseudoinstructions at all? Why not just add our desired pseudoinstructions into the instruction set? (Your answer should consider at least the case of the MOVE $rt, $rs instruction and the case of addi $rt, $rs, 500000.)

  4. (N points) Consider the following boolean function of three variables:

    A B C | Out ================= 0 0 0 | 1 0 0 1 | 0 0 1 0 | 0 0 1 1 | 1 1 0 0 | 0 1 0 1 | 0 1 1 0 | 1 1 1 1 | 1
    1. Write a boolean algebraic expression for this function, using a conjunction (sum) of 3-term products, as we did with a similar function in class.
    2. Simplify your algebraic expression as much as possible.
    3. Draw a circuit implementing this function using AND, OR, and NOT gates. Use as few gates you can.

  5. (N points) Suppose I gave you two 4-choice 1-bit multiplexers plus a pile of miscellaneous AND, OR, and NOT gates. Draw a diagram showing how you could combine the 4-choice multiplexers to create one 8-choice 1-bit multiplexer.

  6. (2 points) Tell me a joke, please.

  7. (6 points) Consider the following story about D latches and flip-flops.

    • In the beginning, Q = 0, D = 1, and C = 0
    • C's value rose to 1
    • D's value fell to 0
    • C's value fell to 0

    Assuming there was a long enough pause between each step to enable the whole circuit to stabilize, draw a timing diagram for this story for each of the following:

    1. The D latch in Figure B.8.2 of the textbook
    2. The D flip-flop in Figure B.8.4
    3. The D flip-flop in Figure B.8.4, but with the NOT gate moved so it goes in front of the C line on the lefthand latch instead of the righthand latch