This exam doesn't quite fit the "short answers all on one page" model, so structure your answers however you wish, but please make an effort to keep your answers and explanations brief. There's nothing here that requires a lengthy explanation.
You may consult your notes, any book, and the Internet. You may not speak with any person other than Jeff Ondich, electronically or otherwise, about the content of this exam. If you obtain relevant information from any source other than yourself, cite your sources clearly.
(12 points) Consider the following caches. Assume that addresses are 32 bits long. Also, as is our custom this term, assume that a "word" consists of 4 bytes.
For each of these caches, answer the following questions.
Draw a diagram of the cache. How many bits of memory does it use? (Please do not include or concern yourself with showing the memory required to implement the least-recently-used eviction strategy.)
Suppose the byte located at each of the following addresses is requested in the indicated order:
47, 645, 656, 48, 130, 655, 995, 49, 655, 128, 1030, 560, 1170, 49, 130
Once this sequence of requests is finished:
Notes: (1) These addresses are byte addresses--so for example, byte 19 is contained in the word starting at address 16. (2) These hit ratios are very low, both because the caches start out empty, and because I have made no effort to make my numbers adhere to the principles of spacial or temporal locality.
(6 points) Suppose that you are on a chip design team, and the people designing the cache system have done simulations of two cache layouts, yielding the following data:
You may assume that the choice between Options A and B has no effect on the clock rate or the performance of any of the other portions of the chip. (That's an unrealistic simplifying assumption, of course, but go ahead and assume it anyway.)
Which option will you choose, and why? (Note that all of the points for this problem will be for the "why" and not the "which".)
(12 points) This part of the exam concerns the first few pages of John von Neumann's First Draft of a Report on the EDVAC. Read it and answer the following questions. For the first three questions, which concern the historical context of this report, you may need to look elsewhere for information.
(10 points) Let's take one more stroll down memory lane to visit our non-pipelined datapath Fig 4.17. As we have noted all along, there's one big unrealistic aspect of this diagram: the separation of Instruction Memory from Data Memory. Of course, you could build a system that works with this separation, but for the reasons outlined by von Neumann in section 2.5 of his Draft, we don't do that. Modern general-purpose computer systems put instructions and data into the same memory module.
For this problem, your job is to show how to modify Fig 4.17 and its operation to accommodate a combined Instruction Memory / Data Memory. You should assume that each instruction takes two clock cycles. During the first clock cycle, the instruction is loaded from the shared memory into an Instruction Register, and during the second cycle, the instruction is executed as usual.
Hand in a modified or redrawn version of Fig 4.17 showing the reorganization required to implement this two-cycle / one-memory datapath. You may add any new logic elements you need, but try to keep your modifications of 4.17 as simple and minimal as possible. You should also make clear how the control needs to be arranged to make the two-cycle process work.
(2 points) No need for any more recommendations of books or music or jokes or movies or anything. Thanks for joining me this term. Have a great break.
