CS 208: Computer Organization & Architecture

Datapath questions

You may work with your classmates on these problems. If you work closely with another person, feel free to submit your work jointly. (Two-person teams maximum.) Submit as PDF via Moodle.

  1. Consider our friend the datapath shown in Figure 4.17 in Patterson and Hennessy, and imagine that we're executing this instruction:

    lw $t0, 16($s0)

    Your job is to print (or edit as a PDF or JPG or...) Figure 4.17 and show the values of as many lines on the datapath as possible. This includes control lines, lines whose values are used during this cycle, lines whose values are not used during this cycle, etc. For lines where we don't have enough knowledge of the circuitry to say, mark them as "DK" (for "don't know").

    You may make the following assumptions:

    • The lw instruction is located at address 0x00400030.
    • For each k from 0 to 31, $k = 0x00001000 * k. (I have chosen this pattern just so you can answer the question "what's in register k?" when you need to know.)
    • For each address N in data memory, Mem[N] (i.e. the byte located at address N) is equal to N % 256. (Again, we just need to know what's in memory, and this silly little pattern answers that question.)
    • When a 32-bit address is input to the data memory, the resulting 32-bit Read Data consists of bytes in little-endian order. Similarly, 32-bit data submitted to Write Data will be written to memory in little-endian form.
    • Assume that we have executed the lw instruction up through the very end of its clock cycle, but that the clock has not yet fallen to end the cycle.

  2. Still using Figure 4.17, suppose the propagation delays of the various elements are: 12 ns for memory, 6 ns for the ALU, 4ns for the adders, 2 ns for the registers, 3 ns for the Control, 3 ns for the ALU Control, 2 ns for each of the multiplexors, 1 ns for the shift left, 1 ns for the sign extend, and 1 ns for any individual gates. Also, assume that the the PC shows the proper output immediately after the trailing clock edge.

    Given these assumptions:

    1. How long after the trailing clock edge does it take for the circuit's values to stabilize (i.e. before the PC input and the two Write Data values are guaranteed to have their correct values)?
    2. What is the fastest clock speed (measured in clock cycles per second, or Hz) this datapath can allow?

  3. Hey look, we're still using Figure 4.17. This time, fill in this chart, with values for MemToReg, ALUSrc, and RegDst for each of the listed instructions:

    opcodeMemToRegALUSrcRegDst
    lw100011
    sw101011
    beq000100
    add000000
    sub000000
    addi001000

    Given this chart, and assuming these six instructions are the only ones you care about, draw the portion of the Control that takes the opcode as input and produces MemToReg, ALUSrc, and RegDst as output.