Submit as a PDF file via Moodle by 3:20PM Friday, October 14. For circuit diagrams and other
pictures, you may draw by hand and scan or photograph the picture for inclusion in your PDF (but please
make sure the resulting image is readable). For problem #1, you may either copy your code into the
PDF or include an asm file with your submission.
This is a an exam. You may consult your notes, any book, and the Internet. You may
not speak with any person other than Jeff Ondich, electronically or otherwise, about the content
of this exam. If you obtain relevant information from any source other than yourself,
cite your sources clearly.
(6 points) Write a MIPS subroutine called sumcubes that computes
the sum of the first N cubes. (For example, if N is 4, the sum would be 1 + 8 + 27 + 64 = 100.)
Your subroutine should assume that N is stored in $a0 at the time it is called, and should store
the sum in $v0 before jumping back to the caller. You may use the mult
instruction. You may assume N is small enough that the sum will fit in 32 bits. (In other words, don't
worry about overflow.)
(6 points) Consider the 32-bit number 0x216CFFE9. What does this number represent if
you interpret it as:
- a two's complement integer?
- a MIPS instruction? (You may find
this chart of op codes handy.)
- a sequence of four Unicode characters from the Latin 1 supplement, represented as a one-byte codepoint for each character?
(this is a badly phrased question, especially if you want to count each byte
as a Unicode codepoint between 0x00 and 0xFF, since Latin 1 is missing some chunks, and doesn't include ASCII)
-
(6 points) Some questions about integers.
- In base ten, what is the value of the largest 32-bit two's complement integer?
- In base ten, what is the value of the smallest 32-bit two's complement integer? (Note that
"smallest" and "largest" refer to position on the number line so, for example, -2 is smaller than
-1, and -3 is smaller than 1.)
- If you have a 32-bit two's complement integer N > 0, and 2*N is small enough to be
representable as a 32-bit two's complement integer, then you can double N by shifting
its two's complement representation left by one bit. Now, suppose N < 0. Does shifting
left double N? If so, explain why. If not, give an example where it fails.
-
(6 points) Consider the MIPS instruction
li $t3, 6
- The Mars assembler treats li as a pseudo-instruction, and converts it into a different MIPS instruction.
What instruction is that?
- For the instruction in part (a), show a diagram of the MIPS instruction, and the values of
each of its fields. (See this intro to instruction formats
for examples of the kind of diagram I'm talking about. If the instruction is an R-format instruction, for
example, show me the contents of all six of its fields; if it's I-format, show me the contents of all four of its fields; etc.)
- If you replace the 6 in our original instruction with 98765 (i.e. li $t3, 98765), Mars converts
the pseudo-instruction into two instructions. What are they?
- Why does Mars convert li $t3, N into a single MIPS instruction for N=6, but into
a pair of instructions for N=98765?
- For which values of N will li $t3, N become just one instruction, and for which values
will it become two?
(6 points) Consider the following boolean function of three variables:
A B C | Out
================
0 0 0 | 1
0 0 1 | 1
0 1 0 | 0
0 1 1 | 1
1 0 0 | 0
1 0 1 | 1
1 1 0 | 1
1 1 1 | 1
- Write a boolean algebraic expression for this function, using a conjunction
(sum) of 3-term products, as we did with a similar function in class.
- Simplify your algebraic expression as much as possible.
- Draw a circuit implementing this function using only NOT gates and 2-input AND and OR gates.
Use as few gates you can.
(4 points) Suppose I gave you two 4-choice 1-bit multiplexers plus a pile of miscellaneous AND, OR, and NOT gates.
Draw a diagram showing how you could combine the 4-choice multiplexers to create one 8-choice 1-bit multiplexer.
(This can be done quite elegantly, so look for the cleanest solution you can think of.)
(2 points) I just finished a book. What should I read next?
(6 points) Consider the following story about D latches and flip-flops.
- In the beginning, Q = 0, D = 1, and C = 0
- C's value rose to 1
- D's value fell to 0
- C's value fell to 0
Assuming there was a long enough pause between each step to enable the whole circuit
to stabilize, draw a timing diagram for this story for each of the following:
- The D latch in Figure B.8.2 of the textbook
- The D flip-flop in Figure B.8.4
- The D flip-flop in Figure B.8.4, but with the NOT gate moved so it goes in front of the
C line on the lefthand latch instead of the righthand latch