CS 208: Computer Organization and Architecture

Implementing the PDP-8, Phase 2: Control

For this part of the PDP-8 implementation, we're going to create portions of the control associated with the datapath pictured here.

Some explanations

• AR = Address Register
• IR = Instruction Register
• EA = Effective Address
• WE = Write Enable. If WE is asserted to 1, then the memory element in question will accept its input as its new value on the falling edge of the current clock cycle.
• The link and accumulator are stored in a single 13-bit register. The various elements that take this register's value as input (the ALU, the AC/L Logic unit, and the Skip Logic unit) all accept this 13-bit quantity as input.
• You will use this datapath clock cycles diagram to guide your design of the control.

Your tasks

• Work in a group of at least 2 people and at most 4.
• Hand in your work either on paper (in class on Friday, November 4) or via the Courses folder. The assignment is due 8:30 AM Friday, November 4.
• Create a table showing all the control lines in each clock cycle implementing the following instructions: JMP A; ISZ A; TAD I A; CMA IAC; SPA SNA.
• Draw a diagram showing the internal structure of the To EA unit. Include explanatory text if you think that will be helpful.
• Draw a diagram showing the internal structure of the Skip Logic unit. Include explanatory text if you think that will be helpful.
• Draw a diagram showing the internal structure of the PCWE unit. What additional input, if any, does the PCWE unit require, and where will it come from?

Have fun, and let me know if you have questions.